library ieee;
use ieee.std_logic_1164.all;

entity fullAdder32_tb is
end entity fullAdder32_tb;

architecture TESTBENCH of fullAdder32_tb is

	component fullAdder32
		port(
			A, B : in bit_vector(31 downto 0);
			Cin : in bit;
			Sum : out bit_vector(31 downto 0);
			Cout : out bit
		);
	end component;
	
	for all : fullAdder32 use entity work.fullAdder32(STRUCTURAL);
	
	signal num1, num2, sum : bit_vector(31 downto 0);
	signal Cin, Cout : bit;
	
	begin
	
	fa32 : fullAdder32 port map (num1, num2, Cin, sum, Cout);
	num1 <= "00000000000000000000000000000000", "11111111111111111111111111111111" after 20 ns, "10001000100010001000100010001000" after 40 ns; 
	num2 <= "00000000000000000000000000000000", "11111111111111111111111111111111" after 20 ns, "00010001000100010001000100010001" after 40 ns;
	Cin <= '0', '1' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns;
	
end architecture TESTBENCH;
	
	